Simulation is playing an increasingly important role in the design and evaluation of current and future high performance computer systems. Sparc-Sulima is an UltraSPARC SMP full-machine simulator currently being developed by the CC-NUMA Project (before that by the ANU-Fujitsu CAP Project). Sparc-Sulima simulates an UltraSPARC processor by interpreting each instruction.
Currently, Sparc-Sulima simulates an SMP by simulating a number of cycles to each CPU in a round-robin fashion. However, with the CC-NUMA project's recent acquisition of a 12 CPU (UltraSPARC III-based) V880 system, it is possible to use the potential parallelism to speed up simulation. The most obvious approach is to run each CPU on a separate thread, which under the Solaris threads model, can be run in parallel on separate CPUs.
As on a real machine, the threads simulating the CPUs would only need to communicate when events corresponding to the (external) cache coherency protocol and main memory access occur. In order to maintain realistic memory system event `interleavings', however, it might be desirable to (loosely) synchronize the threads at such points.
This project involves non-trivial research-level issues. It will involve a careful evaluation of the design of Sparc-Sulima, and how it might be re-adapted for threaded implementation. Locks will need to be designed not only for the simulated external caches and main memory systems, but also for other shared resources, eg. the SolEmn (Solaris system call Emulation) facility, and in particular its implementation of light-weight processes (LWPs). This project is part of the CC-NUMA Project.
Last Modified: Peter Strazdins, 28 Jan 2004