Hons/MIT project proposal(s):
Multithreading Issues on the OpenPower 720 Multiprocessor
supervisor:
Dr Peter Strazdins
A state-of-the-art
OpenPower 720 Multiprocessor has recently be installed at DCS,
courtesy of OzLabs branch of the IBM Linux
Technology Centre.
As a shared memory multiprocessor, it is an interesting system:
- a 2-way SMP (symmetric multiprocessor),
i.e. two independent processors sharing a physical address space,
with a coherency protocol implemented by the bottom-level caches.
- 2 CPU `cores' per SMP node, i.e. two CPUs sharing caches
- 2-way symmetric multithreading (SMT) per core,
i.e. 2 threads (sharing the same address space) can execute
simultaneously on each core; these threads have different register
sets but share all other resources (including the CPU).
The CPU can thus switch rapidly between the threads, e.g.
upon a cache miss
This permits up to 8 threads to execute (effectively) simultaneously
on the system. Another interesting aspect of the OpenPower 720
is it can simultaneously host a number of virtual machines
configurations through a low-level resource manager called the
Hypervisor.
Such a multi-level processor opens interesting possibilities in running
multiple threads. The following themes (which could be expanded tom
projects in their own right) thus emerge:
- investigation and evaluation of fast synchronisation algorithms,
and `lockless' data structures.
- evaluate the system on scientific benchmarks,
includes the
OpenMP Parallel Benchmarks and the
STREAM
benchmarks. Here issues such as the effectiveness of SMT
and non-uniform memory accesses effects are of particular interest.
These projects are of strategic interest not only to DCS but OzLabs as well.
References
See the links above, and also:
-
Maurice Herlihy et al, Dynamic-sized Lockfee Data Structures,
Sun Microsystems technical Report T+R-2002-110 (for theme 1)
-
SMT and use of multiple cores are related to the idea of
chip multithreading (CMT).
Last Modified: Peter Strazdins, 12 Dec 2005