Efficient Cycle-Accurate Simulation of the UltraSPARC III CPU
{Peter Strazdins, Bill Clarke and Andrew Over,
Efficient Cycle-Accurate Simulation of the UltraSPARC III CPU,
in Thirtieth Australasian Computer Science Conference (ACSC2007), Ballarat,
Australia, January 2007, pp 221--228.
(Conferences in Research and Practice in Information Technology (CRPIT),
Vol. 62. Gillian Dobbie, Ed.)
Contents
Abstract
This paper presents a novel technique for cycle-accurate simulation of
the Central Processing Unit (CPU) of a modern superscalar processor, the
UltraSPARC III Cu processor. The technique is based on adding a module
to an existing fetch-decode-execute style of CPU simulator, rather than
the traditional method of fully modelling the CPU
microarchitecture. It is also suitable for accurate SMP modelling. The
main functions of the module are the simulation of instruction grouping,
register interlocks and the store buffer. Its simple table-driven
implementation permits easy modification for exploring
microarchitectural variations. The technique results in a 40% loss
of simulation speed, instead of a 10 times or greater performance loss
by fully implementing the detailed micro-architecture. The technique is
validated against an actual UltraSPARC III Cu processor, and achieves
high levels of accuracy over a range of scientific benchmarks.
Keywords
parallel computing, computer simulation,
execution-driven simulation, validation