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For compatibility with Xilinx FPGA in the hardware labs,
we will use the *IEEE 1164 library*, and in
particular the STD
LOGIC and
STD
LOGIC
VECTOR data types
for our input/output signals.

STD LOGIC is a subtype of STD ULOGIC, and has the following logic values:

Logic value | State | Strength |

U | Uninitialized | - |

X | Unknown | Forcing |

0 | 0 | Forcing |

1 | 1 | Forcing |

Z | - | High Impedance |

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