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Design Flow: Entry, Simulation and Implementation

VHDL is used for a range of purposes, including:

Simulation can be done at different levels, such as

Synthesis refers to the procedure for creating the desired physical implementation of a design, and is part of the design flow. The design flow may involve several levels of simulation, and iteration.

For our purposes in this course the basic design flow will be:

Schematic and/or VHDL design entry

ideal or part-physical simulation


The Xilinx Foundation software tools will be used for design entry, simulation and synthesis.

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ANU Engineering - ENGN3213