Read through these notes thoroughly, and do any additional reading from the textbook and lecture notes to help your understanding.
Complete the schematic/VHDL design and software simulation of the reaction timer. Include design details in your notebooks and paste in schematic/VHDL and simulation printouts.
Keep the schematic/VHDL source files in your computer account so they can be accessed and used in the lab.
Reading: Wakerly, sections 7.4-7.7, 8.1, 8.7-8.9 (for state machine design) and section 8.4.3 (for decade counters and cascading).