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Pins

Using the HDL Editor, create the user constraint file adder4-v.ucf with the pin specifications given in the following table:

  Xilinx Xilinx board Trainer board
signal pin resource resource
M P77 - SW
S P78 - SW
Zin P79 - SW
Zout P61 LED-1 -
A<0> P19 SW3-1 -
A<1> P20 SW3-2 -
A<2> P23 SW3-3 -
A<3> P24 SW3-4 -
B<0> P25 SW3-5 -
B<1> P26 SW3-6 -
B<2> P27 SW3-7 -
B<3> P28 SW3-8 -
F<0> P10 - 7-seg A
F<1> P9 - 7-seg B
F<2> P8 - 7-seg C
F<3> P7 - 7-seg D

Note that you will be using resources on both the Xilinx demo board and on the digital trainer board. Make sure you connect the Xilinx ground to the trainer board ground.


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ANU Engineering - ENGN3213