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Pins

In the design andor we have three inputs and one output, which we map to Xilinx board resources via Xilinx pins as follows:

		xilinx
signal	xilinx pin	board resource
A	P19	SW3-1
B	P20	SW3-2
C	P23	SW3-3
X	P61	LED-D1

The file andor.ucf (user constraint file .ucf) specifies these associations, as follows:

NET A  LOC = P19;
NET B  LOC = P20;
NET C  LOC = P23;
NET X  LOC = P61;

You can view this file using the HDL editor.

A user constraint file with the same name as the project name will be used by default by the software for synthesis and implementation (if other names are used, they must explicitly be referenced).

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