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Creating the Top-Level VHDL Source File

1.

Create a new VHDL file adder4-v.vhd using the HDL Editor. Enter the following code:

-- ENGN3213, adder4-v.vhd
-- Name:    , date:

library IEEE;
use IEEE.std_logic_1164.all;

entity adder4 is
        port( a,b : in std_logic_vector(3 downto 0); Ci : in std_logic;
                s : out std_logic_vector(3 downto 0); Co : out std_logic);
end adder4;

architecture structure of adder4 is
component adder
        port(X,Y,Cin : in std_logic;
                 Cout, Sum : out std_logic);
end component;
signal c : std_logic_vector(3 downto 1);
begin
        fa0: adder port map (a(0), b(0), Ci, c(1), s(0));
        fa1: adder port map (a(1), b(1), c(1), c(2), s(1));
        fa2: adder port map (a(2), b(2), c(2), c(3), s(2));
        fa3: adder port map (a(3), b(3), c(3), Co, s(3));
end structure;

and save in your main project folder adder4-v.

2.

Check the VHDL syntax:

Synthesis $\to$ Check Syntax

3.

Add the VHDL source file adder-v.vhd to the project, e.g. from the project manager window:

Project $\to$ Add Source File(s)..

In this VHDL code, note:

• This is a multi-level file, with top-level entity adder4 and low-level entity adder (used four times).
• The entity adder is a component, and the syntax repeats the port specification.
• This code is structural, since it specifies the circuit as an explicit interconnection of components.
• A signal is used as virtual wireto interconnect the components.
• Some of the input and output signals of adder4 are vectors.

Using the VHDL source files, draw a block diagram of the 4-bit adder showing the interconnections with the 1-bit modules. Compare with the schematic diagram used earlier.

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